We are pleased to advertise a new PhD opportunity, supervised by Dr Qiang Li (email@example.com) and Prof Dave Wallis (firstname.lastname@example.org).
Application deadline: 1 March 2019 Start date: 1 October 2019
In this project, we will develop quantum dot (QD) lasers directly grown on silicon at strategically important 1550 nm emission wavelength. The newly-established metal-organic vapour phase epitaxy (MOVPE) capability and the availability of molecular-beam epitaxy (MBE) provides a complementary experimental setting for this project. Various growth techniques will be investigated with the aim to improve the structural and optical properties of InAs/InP QDs. Challenges associated with integration on silicon will be addressed through development of advanced epitaxial processes including V-groove template assisted epitaxy and cavity confined epitaxy.
Background Today, data has become extremely important in all aspects of human life. Currently data in computers move across chips and from chip to chip electronically, through tiny metal wires. In the context of explosive growth in data traffic, high dissipation electrical-interconnects quickly become the bottleneck due to ohmic loss and RC delays of copper wires. Already, today’s data centres are consuming about 3 percent of the global electricity supply and this number is going to be tripled in the next decade. To address these challenges, silicon photonics is progressing rapidly to realise all-optical interconnects. The use of photon-based communication in integrated circuits allows ultralow power dissipation, low latencies, and unprecedented high bandwidth. However, the lack of an efficient light emitter due to the indirect bandgap properties of silicon continues to pose a major roadblock.
Project aims and methods The project is divided into three stages: •literature review and MOVPE training (0.5 year) •growth of InAs/InP quantum dots and optimisation of the morphology and optical properties (1 year) •develop buffer technology on silicon and enable QD laser device integration (2 years). In Stage 2 and 3, you will interact with a PDRA from Compound Semiconductor Manufacturing Hub who will fabricate devices and provide device feedback.