Building on on going success, the aim of this work package is to demonstrate a UK III V on Si GaN based HFET technology baseline. Specifically targeting wireless applications, this work package aims to ultimately establish a full III V on Si HFET device, a collection of passive devices and a MMIC technology platform suitable for high to medium power microwave 5 G system applications. This work package uses high frequency device characterisation at staged points to allow feedback for the optimisation of the epitaxial growth to reach device performance and a fully integrated on chip technology in line with industrial requirements. This work package activities are closely aligned with major compound semiconductor manufacturing industry partners including Newport Wafer Fab (NWF), IQE, SPTS and the CSA Catapult.
Lead: Prof Khaled Elgaid (ElgaidK@Cardiff.ac.uk)
Overview: The WP 5 focus is to develop advanced GaN on Si RF active and passive devices and implement them through the realisation of high performance MMICs operating at X band and Ka band. The technology development in this WP interacts with other work packages in the CS Manufacturing Hub and strongly links with several key industry partners in areas of both technology and design NWF, SPTS, IQE, MBDA, NTT, Toshiba, CSA Catapult, Leonardo, Huawei Europe and IconicRF.
Progress and Challenges: Typical GaN HFETs for these applications are fabricated on SiC substrates, which are unfortunately limited in size (<150 mm) tend to be very expensive. An alternative solution is to use Si substrates, since these can be very large (>300 mm) and low cost. To date, the RF performance of GaN HFETs fabricated on Si is poor in comparison to those fabricated on SiC due mainly to large lattice mismatch as well as relatively poor thermal conductivity. In addition, the conductivity of Si substrates is not compatible with the realization of low loss passive matching structures needed in MMIC based technology. Irrespective of the substrate used, for high speed/frequency electronic devices and circuits there is the need for short gate lengths (Lg Increase intrinsic transistor performance; hence the requirement of e-beam lithography based 0.25 um) and small source/drain gap <4 μm) to technology. Ensuring a corresponding increase in extrinsic performance requires the appropriate scaling of device parasitics and dimensions for example, a high gate to channel aspect ratio must be maintained. This requires optimization of the epitaxial layer structure and growth. Device layout optimization to minimize capacitive and inductive loading is undertaken using EM modelling supported by RF characterization. Minimization of access resistances requires very low contact resistance, and to address thus, processes such as epitaxial re-growth are being considered A staged approached transitioning from unit cell RF HFET devices, thru RF HFET power bar structures and passive components, to a full HFET MMIC process is envisaged. At each stage, an appropriate Process Development Kit (PDK) allowing the simulation and design of active circuits, will be developed and supplied to end user industrial partners for evaluation and feedback. This will start with 100 mm and move to 200 mm Si substrates.
Advanced RF devices MMIC technology realisation has so far been progressed by developing several fabrication modules taking into account the requirements for a full integrated on chip circuits. This includes active device technology optimisation, epi layer design enhancement and low loss integrated passive device design and development.
Initial activity at Cardiff has focused mainly on defining and acquiring the necessary tool set for both optical and e-beam fabrication of HFET devices. A detailed plan involving the coordination of all RF processing projects, under the leadership of Prof Khaled Elgaid has been implemented with the objective of ensuring that deliverables associated with the development of unit cell RF devices and RF power bars can be achieved. This has resulted in the initial GaN on Si active and passive devices development at Cardiff University and the research team at the Centre of High Frequency Engineering (CHFE) are now in the process of fabricating completed designed MMICs and novel high performance passive devices for on chip integration.
Characterisation capability within the Centre of High Frequency Engineering at Cardiff University has been upgraded to allow for on wafer electrical electrical measurements up to 130 GHz ensuring the ability of full small signal characterization of a device, as well as of its high power nonlinear behaviour.