The approach is to integrate high electron mobility 2DEG with the epitaxial layer structures for all of the analogue and some of the digital electronics.
The 2DEG mobility target is at least 16,000 and up to 18,000 cm2/Vs at room temperature while coupled with high gain transistors for the in-built drive electronics. Epitaxial growth will start on 100mm wafers (year 1), will move to 150mm (year 2). The Hall Magnetic Integrated Circuits (MIC) will be designed to address two options that are inaccessible to silicon, namely high and low gain circuits for very high sensitivities (nanoTesla detection) and high temperature operation (200 °C). The MIC chip fabrication process will focus on high yielding optical lithography, integrated 2μm gate length transistor technology with capabilities in the 10s of GHz, (traditional technology is limited to a few kHz). We aim for Process Development Kits (PDK) for the fabricated circuits on 150mm wafers. Engineering samples (few 100 to 1000s) will permit ample testing to establish statistical variation.
Magnetic testing will use in-house low and high field magnetic set ups to measure all key characteristics of the fully packaged sensors. This will be vital in the initial trials to align parasitic from the packages into the PDK models. Key deliverables from these tests will include sensitivity and linearity, the most critical parameters of the sensors. We will aim for video rate collection using “camera” arrays instead of the current processes, which are entirely manual and highly operator intensive.