Here the emphasis will be on developing fabrication processes on up to 200mm wafers, where possible, compatible across the different materials and devices.
This will involve developing ohmic contacts, gate contacts, via holes, wafer thinning, interconnects, transmission lines and dielectric layers. We will deliver a suite of fully characterised MIM capacitance structures and Cr-Ni meander resistances to enable the realisation of useful on chip circuits (e.g. MMICs), initially on 100mm before moving to 200mm wafers. The challenge is the need to address optical and electronic devices structures and all the associated passive components. For example, in the case of lasers, there is the need for short cavities, facet etching and grating fabrication with tailored recipes for each material. Thus an integrated growth, device fabrication and selective growth technology platform will be developed.
A mixed strategy lithography (wafer scale optical (stepper) and large frame electron beam lithography) will be developed with critical dimension analysis over a large area.
Processing challenges in the GaAs system include the development of multilevel functionality. Here recent work has demonstrated on-chip integrated optoelectronics and capillary fill microfluidics on 2 levels, using standard CS fabrication procedures. The on-chip multilevel functionality must be extended to include control electronics and developed to full wafer size. This also benefits the development of arrays and control electronics in GC 2.
A key generic challenge for III-V on Si fabrication is handling thermal stress cycles during growth and processing. These can be beneficial but also can be harmful and determining acceptable parameter space will be an important outcome of this project. Work will involve iterative cycles of epitaxial growth and fabrication, hence the need for a strong coupling between WP 1 and WP 2 and WP3 and the use of native as well as Si substrates